Analog integrated circuits must rely primarily on capacitors to provide reactances, since traditional IC processes do not allow the fabrication of inductances. The limitations imposed by conventional IC processes on capacitors restrict the type of circuits that can be realized using these processes.
Traditional analog IC processes construct capacitors by sandwiching a dielectric layer between conductors. For example, a polysilicon layer deposited over the silicon substrate can serve as the conductors with a layer of gate oxide as the dielectric. Gate oxide layers are very thin, and hence this type of structure has a very high specific capacitance. Unfortunately, the polysilicon layers and terminals deposited thereon form a MOS structure. This leads to a highly non-linear capacitor unless a large DC bias is maintained across the capacitor. Such biases are incompatible with the low power supply voltages used with modern circuits. Further, MOS capacitors are polarized, and hence, cannot be used in circuits such as switched-capacitor circuits in which the terminals of the capacitor are flipped in polarity.
Capacitors may also be constructed using the metal interconnect layers with a dielectric layer between the metal layers to form a metal-metal capacitor. While such capacitors avoid the problems discussed above with respect to MOS capacitors, metal-metal capacitors have two drawbacks of their own. The interlayer dielectrics are relatively thick; hence, metal-metal capacitors have relatively low specific capacitances. Second, such capacitors suffer from parasitic, or "back-plate" capacitance between one, or both, of the terminals and the substrate of the IC. In most processes, the dielectric thickness between the interconnect layers is roughly equal to the dielectric thickness between the substrate and the bottom interconnect layer. Hence, the parasitic capacitance is roughly equal to the active capacitance.
IC processes having a third layer of metal interconnect have become common. In such processes, a stacked plate structure can be used to provide an improved capacitor structure over the metal-metal structure described above. In this case, the capacitor has two dielectric layers sandwiched between the three metal layers. The outer metal layers are electrically connected to form one terminal of the capacitor, while the middle layer forms the other terminal. This doubles the specific capacitance while leaving the parasitic capacitance approximately the same. Hence, such structures have roughly a 2:1 active to parasitic capacitance ratio. While this represents an improvement over the two-layer capacitor construction, there is still a need for an improved capacitor structure.
Broadly, it is the object of the present invention to provide an improved integrated capacitor structure.
It is a further object of the present invention to provide a capacitor structure that has higher active capacitances than obtainable with prior art metal-metal processes.
It is a still further object of the present invention to provide a capacitor structure that has reduced parasitic capacitance on one of its terminals.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.